Synopsys Internship Program 2018 | BE,B.Tech,ME,M.Tech Freshers Jobs. Synopsys Hiring Freshers For The Position Of Software Intern. Synopsys looking to fill Freshers Jobs Which are vacant In Pune location. Aspirants needs to have Good knowledge of C/C++, Data structures, Algorithms, Unix, XML, HTML and Scripting languages such as Perl along with excellent communication and problem solving skills.
BE,B.Tech,BCA,MCA,ME,M.Tech Freshers Jobs in Synopsys. This is Internship position at Synopsys For Freshers. Aspirants needs to understand that this not a direct off campus drive. You need to apply for this position using the bellow link, once your resume gets shortlisted you will receive confirmation email from the company to attend the drive. Don't forget to practice Synopsys Previous Placement Papers before attending the drive to get select in the interview.
|Job Role||Software Intern|
|Salary||Best In The Marcket|
Synopsys Recruitment Process:
1. Written Test
2. Technical Interview
3. HR Interview
Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure.
- Seeking a highly motivated and innovative engineer.
- Working as part of a highly experienced emulation team, the candidate will be contributing towards improving the quality of Synopsys Synthesis and Emulation tools.
- The position offers an excellent opportunity to work with an expert team of Synthesis and emulation engineers responsible for qualifying the FPGA synthesis tool from specification development to performing functional and performance tests for validating the Synthesis and Emulation tool.
- In addition, this is a great opportunity to work with a wide suite of in-house digital design and verification tools, including VCS, Design Compiler.
- The candidate will be responsible for validation of Emulation tool.
- The Engineer will also design and develop tests in VHDL/Verilog/System Verilog languages to validate the tool.
- Responsible for analyzing benchmarks & in-house, modifying block-level test benches, executing verification plans, debugging RTL and gate-level simulation failures, performing gate-level simulations, interacting with R&D and CAE teams.
Don't Miss The Below Opportunities:
- The successful candidate will have B.Tech / M. Tech with 0-2 years of digital design experience in the industry and hands-on experience in emulation/simulation.
- Knowledge on areas like Synthesis, simulation, verification, place and route, design reuse and/or physical design is preferred.
- Knowledge and experience on Hardware emulation tool or experience in verification technology, testcase creation, simulation using VCS or other simulators, debugging with Verdi/DVE, familiarity with scripting languages is a plus along with good organization and communication skills for interacting with R&D and CAEs teams.
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